

#include "drv_dsp.h"
#ifdef SUPPORT_FM1505_DMS


const reg_config_t dsp_mode2_path_SYS[] = {
    /* SYS Configuration (Base: 0x0FD88250) */
	{0x00000000,	0x000000FF},	//* CORE_IO_SWITCH *//
	{0x00000004,	0x00000000},	//* Reserved *//
	{0x00000008,	0x264102A0},	//* SYS_M_CON1 *//	sys_clk = OSC=32K
	{0x0000000C,	0x00001000},	//0x00004000  //* SYS_M_CON2 *//  16*1024 
	{0x00000010,	0x0000A003},	//* SYS_M_CON3 *//
	{0x00000014,	0x3F880C00},	//* SYS_M_CON4 *// SPI_S/ BCLK_TX0,FRAME_TX0 6mA driving
	{0x00000018,	0x02110800},	//* SYS_M_CON5 *// IRQ and GPIO_INT output, I2S2_TX 6mA driving
};
const size_t dsp_mode2_path_SYS_size = sizeof(dsp_mode2_path_SYS) / sizeof(reg_config_t);

const reg_config_t dsp_mode2_path_AFE[] = {
    // AFE command// base 0x0FD88050
{0x00000000,	0x00000000},  //* AFE_IN1_CON1 *// AECref app, src on, 48k->16k, aec-ref only usage，  
{0x00000004,	0x00000000},  //* AFE_IN1_CON2 *// I2S1_RX input
{0x00000008,	0x00000000},  //* AFE_IN1_CON3 *// 10ms FZ, 2ch, i2s_rx slot0/1
{0x0000000C,	0x00000000},	//* AFE_IN2_CON1 *// VR app, src off, 16k bypass, mic-in usage
{0x00000010,	0x00000000},	//* AFE_IN2_CON2 *// I2S0_RX input
{0x00000014,	0x00000000},	//* AFE_IN2_CON3 *// 10ms FZ, 2ch, i2s_rx slot0/1
{0x00000018,	0x00000000},  //* AFE_IN3_CON1 *//  SRC ref, src off, 16k bypass, mic-in usage  
{0x0000001C,	0x00000000},  //* AFE_IN3_CON2 *//  PDM input	
{0x00000020,	0x00000000},  //* AFE_IN3_CON3 *// 10ms FZ, 4ch, null slot, mic0/1/2/3 enable
{0x00000024,	0x00000000},  //* AFE_IN4_CON1 *//   
{0x00000028,	0x00000000},  //* AFE_IN4_CON2 *// 	   
{0x0000002C,	0x00000000},  //* AFE_IN4_CON3 *//  
{0x00000030,	0x00000000},	//* AFE_IN5_CON1 */
{0x00000034,	0x00000000},	//* AFE_IN5_CON2 */
{0x00000038,	0x00000000},	//* AFE_IN5_CON3 */
{0x0000003C,	0x00000000},	//* AFE_OUT1_CON1 *// 
{0x00000040,	0x00000000},	//* AFE_OUT1_CON2 *// 
{0x00000044,	0x00000000},	//* AFE_OUT1_CON3 *// 
{0x00000048,	0x00000000},  //* AFE_OUT2_CON1 *// VR app, src on, 16k->48k, voice data  
{0x0000004C,	0x00000000},  //* AFE_OUT2_CON2 *// output I2S2_TX
{0x00000050,	0x00000000}, 	//* AFE_OUT2_CON3 *// 10ms FZ, 2ch, i2s_tx slot 0/1 
{0x00000054,	0x00000000},  //* AFE_OUT3_CON1 *//
{0x00000058,	0x00000000},  //* AFE_OUT3_CON2 *//
{0x0000005C,	0x00000000},  //* AFE_OUT3_CON3 *//
{0x00000060,	0x00000000},  //* AFE_OUT4_CON1 */
{0x00000064,	0x00000000},  //* AFE_OUT4_CON2 */
{0x00000068,	0x00000000},  //* AFE_OUT4_CON3 */
{0x0000006C,	0x00000000},  //* AFE_OUT5_CON1 */
{0x00000070,	0x00000000},  //* AFE_OUT5_CON2 */
{0x00000074,	0x00000000},  //* AFE_OUT5_CON3 */
{0x00000078,	0x00000000},	//* AFE_M_I2S1_RX */ // set 2-ch I2S
{0x0000007C,	0x00000000},	//* AFE_M_I2S1_TX */ // set 2-ch I2S
{0x00000080,	0x00000000},	//* AFE_M_I2S2_RX */ // set 2-ch I2S
{0x00000084,	0x00000000},	//* AFE_M_I2S2_TX */ // set 2-ch I2S
{0x00000088,	0x00000000},	//* AFE_M_I2S3_RX *//
{0x0000008C,	0x00000000},	//* AFE_M_I2S3_TX *//
{0x00000090,	0x0C000000},	//* AFE_M_MICS1_CON1 *// SRC clock divider//org 0x0C000400
{0x00000094,	0x00000000},	//* AFE_M_MICS1_CON2 */
{0x00000098,	0x00000000},	//* AFE_M_MICS1_VOL */ // 0dB
{0x0000009C,	0x00000000},	//* AFE_M_MICS2_CON1 */ 
{0x000000A0,	0x00000000},  //* AFE_M_MICS2_CON2 */ 
{0x000000A4,	0x00000000},  //* AFE_M_MICS2_VOL */  
{0x000000A8,	0x00000000},  //* AFE_S1_I2S1_RX */   
{0x000000AC,	0x00000000},  //* AFE_S1_I2S1_TX */   
{0x000000B0,	0x00000000},  //* AFE_S1_I2S2_RX */   
{0x000000B4,	0x00000000},  //* AFE_S1_I2S2_TX */   
{0x000000B8,	0x00000000},  //* AFE_S1_I2S3_RX */   
{0x000000BC,	0x00000000},  //* AFE_S1_I2S3_TX */   
{0x000000C0,	0x00000000},  //* AFE_S1_MICS1_CON1 */
{0x000000C4,	0x00000000},  //* AFE_S1_MICS1_CON2 */
{0x000000C8,	0x00000000},  //* AFE_S1_MICS1_VOL */ 
{0x000000CC,	0x00000000},  //* AFE_S1_MICS2_CON1 */
{0x000000D0,	0x00000000},  //* AFE_S1_MICS2_CON2 */
{0x000000D4,	0x00000000},  //* AFE_S1_MICS2_VOL */ 
{0x000000D8,	0x00000000},  //* AFE_S2_I2S1_RX */   
{0x000000DC,	0x00000000},  //* AFE_S2_I2S1_TX */   
{0x000000E0,	0x00000000},  //* AFE_S2_I2S2_RX */   
{0x000000E4,	0x00000000},  //* AFE_S2_I2S2_TX */   
{0x000000E8,	0x00000000},  //* AFE_S2_I2S3_RX */   
{0x000000EC,	0x00000000},  //* AFE_S2_I2S3_TX */   
{0x000000F0,	0x00000000},  //* AFE_S2_MICS1_CON1 */
{0x000000F4,	0x00000000},  //* AFE_S2_MICS1_CON2 */
{0x000000F8,	0x00000000},  //* AFE_S2_MICS1_VOL */ 
{0x000000FC,	0x00000000},  //* AFE_S2_MICS2_CON1 */
{0x00000100,	0x00000000},  //* AFE_S2_MICS2_CON2 */
{0x00000104,	0x00000000},  //* AFE_S2_MICS2_VOL */ 
{0x00000108,	0x00000000},  //* AFE_S3_I2S1_RX */   
{0x0000010C,	0x00000000},  //* AFE_S3_I2S1_TX */   
{0x00000110,	0x00000000},  //* AFE_S3_I2S2_RX */   
{0x00000114,	0x00000000},  //* AFE_S3_I2S2_TX */   
{0x00000118,	0x00000000},  //* AFE_S3_I2S3_RX */   
{0x0000011C,	0x00000000},  //* AFE_S3_I2S3_TX */   
{0x00000120,	0x00000000},  //* AFE_S3_MICS1_CON1 */
{0x00000124,	0x00000000},  //* AFE_S3_MICS1_CON2 */
{0x00000128,	0x00000000},  //* AFE_S3_MICS1_VOL */ 
{0x0000012C,	0x00000000},  //* AFE_S3_MICS2_CON1 */
{0x00000130,	0x00000000},  //* AFE_S3_MICS2_CON2 */
{0x00000134,	0x00000000},  //* AFE_S3_MICS2_VOL */ 
{0x00000138,	0x00000000},  //* Reserved */         
{0x0000013C,	0x00000000},  //* Reserved */         
{0x00000140,	0x00000000},  //* Reserved */         
{0x00000144,	0x00000000},  //* Reserved */         
{0x00000148,	0x00000000},  //* Reserved */         
{0x0000014C,	0x00000000},	//* AEC_S1_CON *// disable AEC
{0x00000150,	0x00000000},	//* AECS1_REF1_CON */ // I2S1Rx0
{0x00000154,	0x00000000},	//* AECS1_REF2_CON */ // I2S1Rx1
{0x00000158,	0x00000000},  //* AECS1_REF3_CON */ // 
{0x0000015C,	0x00000000},	//* AECS1_REF4_CON */ // 

};

const size_t dsp_mode2_path_AFE_size = sizeof(dsp_mode2_path_AFE) / sizeof(reg_config_t);
#endif
